The present invention relates in general to the field of data transfer controllers which link a host computer with a high speed network. In particular, the data transfer controller allows transfer of data between a network bus in the high speed network and a system bus in the host computer.
Prior art data transfer controllers, and in particular those utilized with local area networks, typically consist of a control microprocessor, a local memory, a direct memory access channel, a host computer interface logic and a dedicated network controller. An internal bus links the microprocessor and the local memory with the direct memory access channel and the interfaces. An access to the local bus is granted through an arbitration scheme as is well known in the art.
The disadvantage to such a method is mainly due to the fact that the bus is shared through multiple users, so effectively the microprocessor is allowed to use its resources only during a fraction of available time. The objectives for the microprocessor are to serve a host protocol, to report a status, to process data, or to perform communications functions above the level of physical access to the network. Because of limited time available to the microprocessor, the overall throughput is significantly low despite high performance levels of individual subunits which form the data transfer controller.
Several solutions have been proposed in the prior art to solve the problem of low throughput. Some of these solutions use a dual port memory connected to the network controller at one port and to the microprocessor and the direct memory access channel at the other port. Despite the additional hardware, the microprocessor is still suspended for a significant period of time in order to allow the direct memory access channel to operate on the local bus.
Another approach to increase the throughput in the prior art is based on the use of large first-in first-out memories installed on input and output ports to the network controller. This method is effective to increase a raw transfer rate of transparent data. The disadvantage to this method is that access to the data by the microprocessor is limited and thus the functionality of the data transfer controller as a whole is limited.
Therefore it is an object of the present invention to obtain high overall throughput combined with unlimited access to transferred data by the onboard microprocessor to overcome the disadvantages in the prior art. The present invention has the advantage of allowing the microprocessor to operate full time without waiting for other users of the resources within the data transfer controller. Since the microprocessor is usually the slowest part of the controller, this feature of the present invention has a direct impact on the overall performance of the controller.